Microcode in Intel's 8087 floating-point chip: the scale instruction

The complex microcode of the 8087’s FSCALE instruction, designed to handle special floating-point cases, reveals that even early coprocessors required extensive, multi-layered logic for numerical robustness.

Researchers have reverse-engineered the microcode of Intel's 8087 floating-point coprocessor, focusing on the FSCALE (Floating-point Scale) instruction. Introduced in 1980, the 8087 made floating-point operations significantly faster and became a de facto standard. The FSCALE instruction, designed for efficiently scaling numbers by powers of two, was found to be surprisingly complex. Instead of a simple operation, it utilizes over 140 micro-instructions and three levels of subroutine calls. This complexity is due to the need to handle numerous special cases, including various number types like infinity, NaN, and denormalized values, as well as exception handling for operations like overflow, underflow, and invalid operands. The reverse-engineering process involved physically dissecting an 8087 chip to examine its microcode ROM and datapath circuitry, revealing the intricate low-level code that governs its high-precision calculations.

The detailed examination of the 8087's FSCALE microcode demonstrates a sophisticated approach to floating-point arithmetic for its time. The instruction’s reliance on over 140 micro-instructions and multiple subroutine calls highlights the significant engineering effort dedicated to achieving numerical accuracy and handling edge cases, such as NaNs and infinities, through masked exceptions.

This deep dive into the 8087's internal workings, particularly the microcode's handling of special values and exceptions, provides a foundational understanding of how early coprocessors managed computational complexity. It underscores the trade-offs between instruction simplicity for programmers and the intricate, robust logic required internally for reliable floating-point operations in diverse computational scenarios.