Samsung and TSMC commit to using ASML's High NA EUV machines by 2028 and 2030, joining Intel, with all four agreeing to shift from 6-inch to 12-inch photomasks
AI Signal Decode
The commitment from Samsung and TSMC to adopt ASML's High-NA EUV machines by 2028 and 2030 respectively is a critical development for the semiconductor industry. This joint adoption by the world's leading foundries, alongside Intel, signals a unified push towards the leading edge of chip manufacturing. High-NA EUV is essential for producing sub-2nm process nodes, which will power next-generation AI accelerators, advanced CPUs, and mobile SoCs. The significant investment required for these machines underscores the intense competition among these giants to secure technological supremacy and meet the escalating demand for increasingly sophisticated chips.
The industry-wide transition to 12-inch photomasks from the current 6-inch standard is a major operational shift that will enhance efficiency and potentially lower costs in the long run. Larger photomasks allow for more die per wafer, improving yield and reducing the per-die manufacturing cost, especially for complex, high-volume chips. This standardization will streamline the supply chain for photomask production and inspection, creating economies of scale for mask makers and lithography equipment suppliers. The move away from 6-inch signifies the obsolescence of older processes for advanced nodes, forcing a comprehensive upgrade across the ecosystem.
The immediate market implication is a significant boost for ASML, solidifying its dominant position in the critical lithography equipment market. For Samsung and TSMC, this investment is a proactive measure to future-proof their manufacturing capabilities and maintain their competitive edge against each other and emerging players. The adoption rate of High-NA EUV will be a key indicator of which foundry can most effectively leverage this new technology for product differentiation and market share gains in the coming years. Investors will closely monitor the capital expenditures and ramp-up timelines announced by these companies.
Looking ahead, the successful integration and yield optimization of High-NA EUV lithography will be paramount. The technical challenges associated with these machines are substantial, and early adopters will face a steep learning curve. Watch for announcements regarding pilot production runs, first-generation chips utilizing this technology, and any potential delays or breakthroughs in process development. The performance gains and cost-effectiveness achieved will determine the pace at which other foundries and IDMs follow suit, potentially creating a new tier of advanced manufacturing capabilities.