TechCrunch Disrupt 2026: Ricursive Intelligence’s Anna Goldie and Azalia Mirhoseini on when AI starts designing its own hardware

The AI hardware design cycle shortens from years to weeks, unlocking new chip architectures.

Ricursive Intelligence, a startup founded in late 2025, is developing artificial intelligence systems designed to automate and accelerate the complex process of chip design. The company's co-founders, Anna Goldie and Azalia Mirhoseini, previously led AlphaChip at Google, an AI that generated chip layouts significantly faster than human designers and contributed to Google's Tensor Processing Units. Ricursive aims to reduce the typical two-to-three-year chip design cycle to mere weeks by creating AI that learns from each design, improving subsequent iterations. The company has already secured $335 million in funding at a $4 billion valuation, with Nvidia as one of its investors. Goldie and Mirhoseini will discuss their approach to closing the loop between AI and chip development at TechCrunch Disrupt 2026, aiming to overcome a major bottleneck in the advancement of AI capabilities.

The implications of AI designing its own hardware are profound, potentially creating a self-improving loop where better AI designs better chips, which in turn enable more powerful AI. This acceleration could dramatically speed up the development of AI capabilities, breaking through current hardware limitations. The market should watch for how this closed-loop system impacts the competitive landscape, potentially giving early adopters a significant advantage in AI performance.

Ricursive's success hinges on its AI's ability to generalize and learn across diverse chip designs, a challenge that could determine the scalability of their approach. If successful, it could disrupt traditional semiconductor design firms and accelerate the pace of innovation across the entire AI industry, from foundational models to specialized applications. Investors and technologists will be observing whether Ricursive can fulfill its promise of rapid, iterative hardware design.