The Intel 8087 chip: floating-point addition and subtraction

If you work with vintage computing hardware, you can now understand the specific internal mechanics of a groundbreaking floating-point coprocessor.

In 1980, Intel released the 8087 math coprocessor, significantly accelerating floating-point calculations for systems like the IBM PC. This article delves into the chip's internal workings, specifically its implementation of floating-point addition and subtraction. The 8087 achieved its speed by using specialized circuitry, including an integer adder and a versatile shifter, to manipulate 80-bit "temporary real" floating-point numbers. The process involves aligning the binary points of the operands, performing integer addition or subtraction on their significands, and then normalizing the result by adjusting the exponent and significand. The chip manages numerous special cases for values like infinities and NaNs, employing an internal register stack and tag system to track data types and states. The microcode, stored in a dedicated ROM, orchestrates these operations through a sequence of low-level instructions.

The 8087's design prioritized performance through dedicated hardware, such as a 69-bit integer adder and a bit shifter capable of arbitrary shifts, essential for aligning floating-point significands. Its internal "temporary real" format, an 80-bit representation, allowed for both a vast range of numbers (over 10^4932) and high precision due to a 64-bit significand. The use of microcode to implement complex operations highlights a common architectural approach for handling specialized functions efficiently in early processors.

The article's detailed examination of the 8087's microcode and circuitry, including the register stack and tag system, provides crucial insight into how early processors managed the complexities of floating-point arithmetic, including edge cases like infinities and zeros. This level of reverse engineering offers valuable historical data for understanding the evolution of computational hardware and the engineering trade-offs made to achieve significant performance gains.