ASML and TSMC want bigger masks for smaller chips
AI Signal Decode
The core of the initiative lies in addressing the limitations imposed by ASML's anamorphic optical design in its initial high-NA EUV lithography systems. This design, intended to maintain compatibility with existing 6-inch masks, results in an exposure field half the size of previous generations. Consequently, chip designs exceeding this field require 'stitching' – exposing and combining multiple patterns – which introduces complexity, potential defects, and reduced fab productivity. The proposed move to 12-inch masks will restore the full exposure field, thereby eliminating the need for stitching for larger dies and streamlining the manufacturing process for next-generation chips.
Market implications of this transition are substantial. A 12-inch mask format promises increased scanner productivity and lower manufacturing costs per chip, which is vital as chipmakers push towards smaller process nodes and more complex transistor architectures fueled by AI demand. TSMC's intention to deploy high-NA EUV for advanced nodes by 2030, and Samsung's plan for DRAM by 2028, highlight the aggressive timeline. This move will necessitate significant investment in new mask infrastructure and supply chain adjustments, requiring close collaboration between equipment manufacturers, mask shops, and chip designers to ensure process alignment.
Technically, the adoption of 12-inch masks represents a necessary evolution to fully leverage the capabilities of high-NA EUV lithography. While ASML's current high-NA systems can operate with 6-inch masks, the larger format is essential for optimizing scanner efficiency and enabling the production of increasingly larger and more intricate semiconductor designs. This aligns with IDC's assessment that the transition is a fundamental step, akin to the shift from 200mm to 300mm wafers, emphasizing the need for broad industry participation and technological synchronization across the entire semiconductor ecosystem.
Looking ahead, the key factors to watch will be the progress of the 12-inch mask pilot lines, scheduled for 2031, and the industry's ability to align processes and technologies by the 2033 production readiness target. The willingness of toolmakers to develop supporting infrastructure and the successful integration of these larger masks into existing high-volume manufacturing flows will be critical. Furthermore, the impact on AI chip development and the potential for cost reductions will be closely monitored as this new lithography paradigm matures.